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CXP83620/83624 CXP83621/83625
CMOS 8-bit Single Chip Microcomputer
Description The CXP83620/83624 and the CXP83621/83625 are CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, sub timer/counter, LCD controller/driver and remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP83620/83624 and the CXP83621/83625 also provide a sleep/stop function that enables lower power consumption. CXP83620/83624 80 pin QFP (Plastic) 80 pin LQFP (Plastic)
Features * Wide-range instruction system (213 instructions) to cover various types of data. -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V) 1s at 4MHz operation (2.7 to 5.5V) 122s at 32kHz operation (2.7 to 5.5V) * Incorporated ROM capacity 20K bytes (CXP83620, 83621) 24K bytes (CXP83624, 83625) * Incorporated RAM capacity 736 bytes (includes LCD display data area and serial interface RAM) * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 12.4s/10MHz) -- Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type (MSB/LSB first selectable), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer, Sub timer/counter -- LCD controller/driver Maximum 128 segment display possible (during 1/4 duty) 4 common output, 32 segment output Display method static, 1/2, 1/3, 1/4 duty Bias method 1/2, 1/3 bias -- Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO * Interruption 14 factors, 14 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 80-pin plastic QFP/LQFP * Piggy/evaluation chip CXP83600 (CXP83620, 83624) CXP83601 (CXP83621, 83625) Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP83621/83625 80 pin QFP (Plastic)
-1-
E98134B96
Block Diagram
TEX
EXTAL
TX
XTAL VDD Vss RST
SPC700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
SEG0 to SEG31
32
PORT A
AN0 to AN7
8
A/D CONVERTER
INT0 INT1 INT2 INT3 INT4
8
PA0 to PA7
LCD CONTROLLER/ DRIVER ROM 20K/24K BYTES RAM 736 BYTES
PORT B
COM0 to COM3
4
8
PB0 to PB7
INTERRUPT CONTROLLER
RMC FIFO
REMOCON
PORT C
VL VLC1 VLC2 VLC3
8
PC0 to PC7
PORT D
8
PD0 to PD7
CS0 SI0 SO0 SCK0 BUFFER RAM 2 PRESCALER/ TIME-BASE TIMER
SUB TIMER/ COUNTER
PORT E
SI1 SO1 SCK1
EC
8-BIT TIMER/COUNTER 0
PORT F
ADJ
3
PORT H
PORT I
-2-
SERIAL INTERFACE UNIT (CH0)
5 2
PE0 to PE4 PE5 to PE6
SERIAL INTERFACE UNIT (CH1)
8
PF0 to PF7
TO
1
8-BIT TIMER 1
PH0
CXP83620/83624, CXP83621/83625
2
PI0 to PI1
CXP83620/83624, CXP83621/83625
Pin Assignment (Top View) CXP83620/83624 (QFP package)
PE0/INT0/EC
PE2/INT2
PE1/INT1
PF7/SEG31
PF6/SEG30
PI1/TEX
PI0/TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE3/INT3 PE4/RMC PE5/TO PE6/ADJ PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/INT4 PA0/AN0 PA1/AN1 PA2/AN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3
NC
VDD
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24 COM1
PA3/AN3
Note) Do not make any connections to NC (Pin 75).
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
EXTAL
-3-
COM0
COM2
XTAL
VLC3
VLC2
VLC1
VSS
RST
VL
PD7/SEG23
CXP83620/83624, CXP83621/83625
Pin Assignment (Top View) CXP83620/83624 (LQFP package)
PE0/INT0/EC
PE4/RMC
PE3/INT3
PE2/INT2
PE1/INT1
PF7/SEG31
PF6/SEG30
PI1/TEX
PI0/TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC
VDD
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PE5/TO PE6/ADJ PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/INT4 PA0/AN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
PA1/AN1
PA2/AN2
Note) Do not make any connections to NC (Pin 73).
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
EXTAL
-4-
COM0
COM1
COM2
COM3
SEG0
XTAL
VLC3
VLC2
VLC1
RST
VSS
VL
CXP83620/83624, CXP83621/83625
Pin Assignment (Top View) CXP83621/83625 (QFP package)
PE0/INT0/EC
PE4/RMC
PE3/INT3
PE2/INT2
PE1/INT1
PF7/SEG31
PF6/SEG30
PI1/TEX
PI0/TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC
VDD
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PE5/TO PE6/ADJ PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/INT4 PA0/AN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
PA1/AN1
PA2/AN2
Note) Do not make any connections to NC (Pin 73).
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
EXTAL
-5-
COM0
COM1
COM2
COM3
SEG0
XTAL
VLC3
VLC2
VLC1
RST
VSS
VL
CXP83620/83624, CXP83621/83625
Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a bit unit. Standby release input can be set in a bit unit. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/Analog input
Analog inputs to A/D converter. (8 pins)
PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port B) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) External event inputs for 8-bit timer/counter. (Port E) 7-bit port. Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) External interruption request inputs. (4 pins) Remote control reception circuit input. Output for 8-bit timer/counter rectangular wave. Output for TEX oscillation frequency division. (Port H) 1-bit I/O port. Incorporation of pull-up resistor can be set through the program. (1 pin) (Port I) 2-bit input port. (2 pins)
PC0 to PC7
I/O
PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3 PE4/RMC PE5/TO PE6/ADJ
Input/Input/Input Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output
PH0/INT4
I/O/Input
External interruption request input. (1 pin)
PI0/TX PI1/TEX
Input Input/Input
Crystal connectors for sub timer/counter clock oscillation. For usage as event counter, input to TEX, and leave TX open.
-6-
CXP83620/83624, CXP83621/83625
Symbol PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 SEG0 to SEG15 COM0 to COM3 VLC1 to VLC3 VL EXTAL XTAL RST NC VDD VSS Input
I/O Output/Output (Port D) 8-bit output port. (8 pins) (Port F) 8-bit output port. (8 pins)
Functions
LCD segment signal outputs. (16 pins)
Output/Output Output Output
LCD segment signal output. (16 pins) LCD common signal output. (4 pins) LCD bias power supply. (3 pins)
Output Input
Control pin to cut off the current flowing to external LCD bias resistor during standby. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active system reset. NC. Do not make any connections to NC. Positive power supply. GND.
-7-
CXP83620/83624, CXP83621/83625
I/O Circuit Format for Pins Pin Port A
Pull-up resistor "0" after a reset Port A data
Circuit format
After a reset
PA0/AN0 to PA7/AN7
Port A direction "0" after a reset Internal data bus RD (Port A) Port A function select "0" after a reset Standby release Edge detection circuit Input multiplexer A/D converter IP Input protection circuit
Hi-Z
8 pins Port B
Pull-up resistor "0" after a reset Port B data
Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V)
PB0
Port B direction "0" after a reset Internal data bus RD (Port B) Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V) IP
Hi-Z
1 pin Port B
Pull-up resistor "0" after a reset Port B data
PB1/CS0 PB3/SI0 PB6/SI1
Port B direction "0" after a reset Internal data bus RD (Port B) CS0 SI0 SI1 Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V) Schmitt input IP
Hi-Z
3 pins
-8-
CXP83620/83624, CXP83621/83625
Pin Port B
Pull-up resistor "0" after a reset Output buffer capability "0" after a reset SCK out Serial clock output ebable Port B function select "0" after a reset Port B data Port B direction "0" after a reset Internal data bus RD (Port B)
Circuit format
After a reset
PB2/SCK0 PB5/SCK1
Hi-Z
IP
Schmitt input
2 pins
SCK in
Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V)
Port B
Pull-up resistor "0" after a reset Output buffer capability "0" after a reset SO Serial data output ebable Port B function select "0" after a reset Port B data Port B direction "0" after a reset Internal data bus RD (Port B) Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V) IP
PB4/SO0 PB7/SO1
Hi-Z
2 pins Port C
Pull-up resistor "0" after a reset Port C data
2
PC0 to PC7
Port C direction "0" after a reset Internal data bus RD (Port C)
1 IP
Hi-Z
1 High current drive 2 Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V) 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 2.7 to 3.3V)
8 pins
-9-
CXP83620/83624, CXP83621/83625
Pin PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3 PE4/RMC 5 pins Port E
TO Port E function select "0" after a reset
Circuit format Port E
Schmitt input IP INT0/EC INT1 INT2 INT3 RMC Internal data bus RD (Port E)
After a reset
Hi-Z
PE5/TO
Port E data "1" after a reset Internal data bus
High level
1 pin Port E
RD (Port E)
Internal reset signal Port E data "1" after a reset 1 ADJ32K ADJ16K 00 MPX 01 10 11
2
PE6/ADJ
ADJ2K Port E function select (upper) Port E function select (lower) "00" after a reset Internal data bus RD (Port E)
1 pin Port H
Pull-up resistor "0" after a reset Port H data
1 ADJ signals are frequency driver outputs for TEX oscillation frequency adjustment. ADJ2K provides usage as buzzer output. 2 Pull-up transistor approx. 150k (VDD = 4.5 to 5.5V) approx. 200k (VDD = 2.7 to 3.3V)
High level High level at ON resistance of pull-up transistor during a reset.
PH0/INT4
Port H direction "0" after a reset Internal data bus RD (Port H) Schmitt input IP
Hi-Z
1 pin
INT4
Pull-up transistor approx. 100k (VDD = 4.5 to 5.5V) approx. 150k (VDD = 2.7 to 3.3V)
- 10 -
CXP83620/83624, CXP83621/83625
Pin Port I
Circuit format
TEX oscillation control circuit "1" after a reset Internal data bus RD (Port I) Internal data bus
After a reset
PI0/TX PI1/TEX
PI1/TEX IP IP
RD (Port I) Schmitt input Clock input
Oscillation halted port input
2 pins
PI0/TX
Port D PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 Port F
Port D, F data
Port/segment output select "0" after a reset
Segment Output (VDD level)
Segment driver
Segment data
16 pins Segment
VCH
SEG0 to SEG15 VDD level 16 pins Common
VDD VCL
VLC1
COM0 to COM3 VDD level
VLC2
VLC3
4 pins
- 11 -
CXP83620/83624, CXP83621/83625
Pin
Circuit format
After a reset
VL
LCD control (DSP bit) "0" after a reset
Hi-Z
1 pin
EXTAL XTAL
* Diagram shows circuit composition during oscillation. EXTAL IP IP * Feedback resistor is removed during stop. XTAL becomes high level.
Oscillation
2 pins
XTAL
Pull-up resistor
RST
Mask option OP IP
Low level (during a reset)
Schmitt input
1 pin
- 12 -
CXP83620/83624, CXP83621/83625
Absolute Maximum Ratings Item Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Symbol VDD Rating -0.3 to +7.0 Unit V V V V mA mA mA mA mA C C mW mW mW QFP-80P-L01 LQFP-80P-L01 QFP-80P-L03 Output per pin Total for all output pins Remarks
(Vss = 0V)
VLC1, VLC2, -0.3 to +7.01 VLC3 VIN VOUT IOH IOH IOL IOLC IOL Topr Tstg -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 600
Value per pin, excluding high current output pins Value per pin for high current output pins2 Total for all output pins
Allowable power dissipation
PD
380 380
1 VIN and VOUT must not exceed VDD + 0.3V. 2 The high current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
- 13 -
CXP83620/83624, CXP83621/83625
Recommended Operating Conditions Item Symbol Min. 4.5 2.7 Supply voltage VDD 2.7 2.7 2.5 VLC1 LCD bias voltage VLC2 VLC3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature 1 2 3 4 5 VILS VILEX Topr 0.7VDD 0.8VDD VDD VDD V V V V V V C 1 Hysteresis input2 EXTAL3, TEX5 1 Hysteresis input2 EXTAL3, TEX5 Vss VDD V LCD power supply range4 Max. 5.5 5.5 5.5 5.5 5.5 V Unit Remarks
(Vss = 0V)
fc = 10MHz or less Guaranteed operation range during 1/2 and 1/4 frequency fc = 4MHz or less dividing mode Guaranteed operation range during 1/16 frequency dividing mode or sleep mode Guaranteed operation range with TEX clock Guaranteed data hold range during stop
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
Value for each pin of normal input ports (PA, PB0, PB4, PB7, PC and PI). Value of the following pins; RST, CS0, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3, INT4 and RMC. Specifies only during external clock input. Optimal values are determined by LCD used. Specifies only during external event count input.
- 14 -
CXP83620/83624, CXP83621/83625
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item Symbol Pins SCK01, SO01 SCK11, SO11 PA, PB, PC, PD2, PE5, PE6, PF2, PH0, VL (VOL only) PC IIHE IILE IIHT Input current IILT IILR IIL IIH I/O leakage current Common output impedance Segment output impedance IIZ RST3 VDD = 5.5V VIL = 0.4V TEX EXTAL Conditions VDD = 4.5V, IOH = -1.0mA VDD = 4.5V, IOH = -2.4mA VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V) Min. 4.0 3.5 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 -45 -2.78 10 Typ. Max. Unit V V V V V V V V A A A A A A A
High level VOH output voltage
Low level VOL output voltage
PA to PC4, PE0 to PE4, VDD = 4.5V, VIH = 4.0V PH4, PI, VDD = 5.5V RST3 VI = 0, 5.5V COM0 to COM3 SEG0 to SEG15, SEG16 to SEG312
RCOM
3 VDD = 5V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V
5
k
RSEG
5
15
k
IDD1
High-speed mode operation (1/2 frequency dividing clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode VDD
12
40
mA
Supply current5
IDDS1
VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Stop mode
2.6
8
mA
IDDS3
VDD = 5.5V, 10MHz and termination of TEX oscillation
10
A
- 15 -
CXP83620/83624, CXP83621/83625
Item
Symbol
Pins
Conditions
Min.
Typ. 10
Max. 20
Unit pF
Input capacity CIN
Clock 1MHz PA to PC, PE0 to PE4, PH, 0V for all pins excluding PI, EXTAL, RST measured pins
1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high. 2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. 3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 5 When all output pins are left open.
- 16 -
CXP83620/83624, CXP83621/83625
Electrical Characteristics DC Characteristics (VDD = 2.7 to 3.3V) Item Symbol Pins Conditions SCK01, SO01 VDD = 2.7V, IOH = -0.24mA SCK11, SO11 VDD = 2.7V, IOH = -0.90mA PA, PB, PC, PD2, PE5, PE6, PF2, PH0, VL (VOL only) PC IIHE IILE IIHT Input current IILT IILR IIL IIH I/O leakage current Common output impedance Segment output impedance IIZ EXTAL VDD = 2.7V, IOH = -0.12mA VDD = 2.7V, IOH = -0.45mA VDD = 2.7V, IOL = 1.0mA VDD = 2.7V, IOL = 1.4mA VDD = 2.7V, IOL = 4.5mA VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL = 0.3V VDD = 3.3V, VIH = 3.3V VDD = 3.3V VIL = 0.3V 0.3 -0.3 0.1 -0.1 RST3 -0.9 (Ta = -20 to +75C, Vss = 0V) Min. 2.5 2.1 2.5 2.1 0.25 0.4 0.9 20 -20 10 -10 -200 -20 0.9 10 Typ. Max. Unit V V V V V V V V A A A A A A A
High level output voltage VOH
Low level VOL output voltage
TEX
PA to PC4, PE0 to PE4, VDD = 2.7V, VIH = 2.4V PH4, PI, VDD = 3.3V RST3 VI = 0, 3.3V COM0 to COM3 SEG0 to SEG15, SEG16 to SEG312
RCOM
4.5 VDD = 3V VLC1 = 2.25V VLC2 = 1.5V VLC3 = 0.75V
7.5
k
RSEG
10
30
k
IDD1
High-speed mode operation (1/2 frequency dividing clock) VDD = 3.3V, 4MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, TEX6 crystal oscillation (C1 = C2 = 47pF) Sleep mode VDD
2.5
8
mA
IDD2 Supply current5
30
100
A
IDDS1
VDD = 3.3V, 4MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, TEX6 crystal oscillation (C1 = C2 = 47pF) Stop mode
0.6
2
mA
IDDS2
16
30
A
IDDS3
VDD = 3.3V, 4MHz and termination of TEX oscillation
10
A
- 17 -
CXP83620/83624, CXP83621/83625
Item
Symbol
Pins
Conditions
Min.
Typ. 10
Max. 20
Unit pF
Input capacity CIN
Clock 1MHz PA to PC, PE0 to PE4, PH, 0V for all pins excluding PI, EXTAL, RST measured pins
1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high. 2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. 3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. 5 When all output pins are left open. 6 The value when 32.768kHz oscillator is connected to TEX.
- 18 -
CXP83620/83624, CXP83621/83625
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time 1 control register (CLC: 00FEh). Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 VDD = 4.5 to 5.5V Min. 1 1 37.5 77.5 200 ns ns 20 ms Typ. Max. 10 5 ns Unit MHz
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
Fig. 1, Fig. 2 VDD = 4.5 to 5.5V external clock drive Fig. 1, Fig. 2 external clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3
tsys + 501
32.768
kHz
tTL, tTH tTR, tTF
10 20
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11").
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation External clock TEX clock applied condition Crystal oscillation
EXTAL
XTAL C2
EXTAL
XTAL
TEX
TX
C1
74HC04
C1
C2
Fig. 2. Clock applied conditions
0.8VDD 0.2VDD
TEX EC
tEH tTH
tEF tTF
tEL tTL
tER tTR
Fig. 3. Event count clock timing - 19 -
CXP83620/83624, CXP83621/83625
(2) Serial transfer (CH0) Item CS SCK delay time CS SCK float delay time CS SO delay time CS SO float delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0 SCK0 SO0 Conditions
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK tDCSKF tDCSO
Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSOF SO0 tWHCS tKCY tKH tKL tSIK tKSI tKSO
CS0 SCK0
SCK0
Input mode Output mode
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
SI0
SCK input mode SCK output mode
SI0
SCK input mode SCK output mode
SO0
SCK input mode SCK output mode
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively. Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to normal.
- 20 -
CXP83620/83624, CXP83621/83625
Serial transfer (CH0) Item CS SCK delay time CS SCK float delay time CS SO delay time CS SO float delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0 SCK0 SO0 Conditions
(Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V) Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns
tDCSK tDCSKF tDCSO
Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode
tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSOF SO0 tWHCS tKCY tKH tKL tSIK tKSI tKSO
CS0 SCK0
SCK0
Input mode Output mode
tsys + 100
8000/fc - 150 -tsys + 100 200 2tsys + 100 100
SI0
SCK input mode SCK output mode
SI0
SCK input mode SCK output mode
SO0
SCK input mode SCK output mode
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively. Note 3) The load condition for the SCK output mode, SO output delay time is 50pF. Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to high.
- 21 -
CXP83620/83624, CXP83621/83625
tWHCS
CS0 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
Fig. 4. Serial transfer CH0 timing
- 22 -
CXP83620/83624, CXP83621/83625
Serial Transfer (CH1) Item SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode SCK1 Input mode Output mode SI1 SCK input mode SCK output mode SI1 SCK input mode SCK output mode SO1 SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively. Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to normal. Serial Transfer (CH1) Item SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK1 (Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V) Conditions Input mode Output mode SCK1 Input mode Output mode SI1 SCK input mode SCK output mode SI1 SCK input mode SCK output mode SO1 SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 100 100 200 200 100 250 125 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively. Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF. Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to high. - 23 -
CXP83620/83624, CXP83621/83625
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
Fig. 5. Serial transfer CH1 timing
- 24 -
CXP83620/83624, CXP83621/83625
(3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = 0V Symbol Pin Conditions
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Min. Typ. Max. 8 3 -10 4910 31/fADC3 10/fADC3 10 4970 70 5030 Unit Bits LSB mV mV s s VDD V
tCONV tSAMP
VIAN AN0 to AN7
0
(Ta = -20 to +75C, VDD = 2.7 to 3.3V, Vss = 0V) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Ta = 25C VDD = 2.7V VSS = 0V -10 2651 31/fADC3 10/fADC3 AN0 to AN7 0 VDD 11 2688 Symbol Pin Conditions Min. Typ. Max. 8 3 40 2716 Unit Bits LSB mV mV s s V
tCONV tSAMP
VIAN
FFh FEh
Digital conversion value
Linearity error 01h 00h VZT Analog input VFT
1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. 2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. 3 fADC = fc/4
Fig. 6. Definition of A/D converter terms
- 25 -
CXP83620/83624, CXP83621/83625
(4) Interruption, reset input Item Symbol
(Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 INT3 INT4 RST Conditions Min. Max. Unit
External interruption high and low level widths
tIH tIL tRSL
1
s
Reset input low level width
32/fc
s
tIH
tIL
0.8VDD INT0 INT1 INT2 INT3 INT4 0.2VDD tIL tIH
Fig. 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. RST input timing
- 26 -
CXP83620/83624, CXP83621/83625
Appendix
(i) Main clock
(ii) Main clock
(iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2 C1 C2
C1
C2
Fig. 9. SPC700 series recommended oscillation circuit Circuit example
Manufacturer
Model CSA4.19MG CSA8.00MG
fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19
C1 (pF) 100 30 30 100 30 30 22 15 10 33 18 15
C2 (pF) 100 30 30 100 30 30 22 15 10 33 18 15
Rd () 0 0 0 0 0 0 1.0k 100 100 2.2k 0 0
Remarks
(i)
MURATA MFG CO., LTD.
CSA10.0MT CST4.19MGW1 CST8.00MTW1 CST10.00MTW1
(ii) (i)
RIVER ELETEC CO., LTD.
HC-49/U03
8.00 10.00 4.19
CL = 12.0pF CL = 12.0pF CL = 12.0pF
KINSEKI LTD.
CX-5F FCR4.19MC51 FCR8.0MC51
8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 32.768 75.00
30 ( 20%) 30( 20%) 20 ( 20%) 20( 20%) 20 ( 20%) 20( 20%) 36 ( 20%) 36( 20%) 20 ( 20%) 20( 20%) 20 ( 20%) 20( 20%) 18 4 18 4 330k 100k (iii) CL = 12.5pF CL = 6.0pF 0 (ii)
TDK Corporation
FCR10.0MC51 CCR4.19MC31 CCR8.0MC51 CCR10.0MC51
VTC-200 Seiko Instruments Inc. SP-T
1 Those marked with an 1 signify types with built-in ground capacitance (C1, C2). Mask Option Table Item Reset pin pull-up resistor Package List Product name CXP83620/83624 CXP83621/83625 Non-existent
FCR: Lead-type ceramic oscillator CCR: Surface mounted-type ceramic oscillator CL : Load Capacitor Content Existent
Package 80-pin plastic QFP/LQFP 80-pin plastic QFP (0.65mm pitch) - 27 -
CXP83620/83624, CXP83621/83625
Characteristics Curve
IDD vs. VDD
(fc = 10MHz, Ta = 25C, typical) 10.0 5.0 1/2 frequency dividing mode 1/4 frequency dividing mode
IDD - Supply current [mA]
1/16 frequency dividing mode Sleep mode
1.0 0.5
0.1 (100A) 0.05 (50A)
32kHz mode (instruction) 32kHz Sleep mode
0.01 (10A) 1
2
3
4
5
6
7
VDD - Supply voltage [V]
IDD vs. fc
(VDD = 5V, Ta = 25C, typical) 15
IDD - Supply current [mA]
10
1/2 frequency dividing mode
1/4 frequency dividing mode 5
1/16 frequency dividing mode Sleep mode
0 0 5 fc - System clock [MHz] 10
- 28 -
CXP83620/83624, CXP83621/83625
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
CXP83620/83624
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8 0.2 M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
QFP-80P-L01 QFP080-P-1420
CXP83620/83624
80PIN LQFP (PLASTIC)
14.0 0.2 60 61 12.0 0.1 41 40
A
80 1 + 0.08 0.18 - 0.03 20
21 (0.22)
0.5
0.13 M
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 LQFP080-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g
- 29 -
0.5 0.2
(13.0)
0.8 0.2
1
24
16.3
CXP83620/83624, CXP83621/83625
CXP83621/83625
80PIN QFP (PLASTIC)
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40
16.0 0.4 + 0.4 14.0 - 0.1 60 61
80 1 0.65 20 0.24
21
+ 0.15 0.1 - 0.1
M 0 to 10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 QFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g
- 30 -
0.5 0.2
+ 0.15 0.3 - 0.1
(15.0)

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